(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to improve the profile of a contact or via hole defined in an insulator layer.
(2) Description of Prior Art
Micro-miniaturization, or the ability to fabricate semiconductor devices with sub-micron features, has allowed the performance of semiconductor devices to be increased while the processing costs for semiconductor chips comprised with devices formed with these same sub-micron features have been reduced. Smaller device features have resulted in a reduction of performance degrading, parasitic junction capacitances. In addition the use of sub-micron features allow a larger number of smaller semiconductor chips to be obtained from a specific size starting semiconductor substrate thus reducing the processing costs for a specific semiconductor chip. The smaller semiconductor chips comprised with sub-micron features still supply device densities equal to, or greater than, counterpart semiconductor chips comprised with larger device features.
The use of sub-micron features can however present difficulties in specific areas of the semiconductor device fabrication procedure. For example the definition of contact holes used to expose an active device region, or the definition of a via hole used to expose an underlying metal structure, can be difficult to achieve for sub-micron diameter openings, (contact/via holes). The desired narrow diameter opening demands a near vertical profile to allow a maximum of underlying contact area to be exposed, in contrast to a contact hole with a tapered profile in which area of the exposed underlying conductive region has been reduced as a result of the unwanted tapered profile. The reduction in exposed area will deleteriously influence the contact or interface resistance generated at the interface of a metal structure in the contact/via opening and the underlying conductive region. In addition, to terminate the contact/via opening dry etch procedure, an etch chemistry selectively terminating at the underlying conductive region has to be employed, usually resulting in formation of polymer layer, which in turn deleteriously influences the ability to define a sub-micron diameter, vertical profile, for the contact/via opening.
This invention will describe a procedure in which a novel, in situ polymer deposition, and polymer removal cycle, is performed after definition of the contact/via opening in an insulator layer, with this novel, in situ deposition and removal procedure, modifying a tapered profile shape to a more vertical profile shape. Prior art such as Sorlis in U.S. Pat. No. 5,851,302, as well as Yeh in U.S. Pat. No. 6,130,166, describe methods of removing polymer and photoresist after definition of specific openings, however these prior arts do not describe the novel procedure described in the present invention in which a tapered profile shape of a contact/via opening is modified to a more vertical profile, via a post-definition, intentional deposition of additional polymer followed by an in situ removal step.